/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 *  \file     Xtal_Reg.h                                                                                *
 *  \brief    This file contains interface header for MCU MCAL driver, ...                              *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2023/08/03     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/

#ifndef XTAL_REG_H
#define XTAL_REG_H

#ifdef __cplusplus
extern "C" {
#endif
/********************************************************************************************************
 *                                 Global Macro definition                                              *
 *******************************************************************************************************/
/* FS32k*/
/* #define FS_GLB_CTL_OFF  0x0U */

/* #define RC_CTL_OFF  0x10U */

/* #define RC_RES_OFF  0x14U */

/* #define XTAL_CTL_OFF  0x20U */

#define BM_XTAL_CTL_DS  ((uint32)0x01U << 4U)

/* #define XTAL_RES_OFF  0x24U */

#define LPVD_CTL_OFF  0x30U

#define FM_LPVD_CTL_ATEST_SEL  ((uint32)0x7U << 12U)
#define FV_LPVD_CTL_ATEST_SEL(v) \
  (((uint32)(v) << 12U) & FM_LPVD_CTL_ATEST_SEL)
#define GFV_LPVD_CTL_ATEST_SEL(v) \
  (((uint32)(v) & FM_LPVD_CTL_ATEST_SEL) >> 12U)

#define FM_LPVD_CTL_TRIM  ((uint32)0xfU << 1U)
#define FV_LPVD_CTL_TRIM(v) \
  (((uint32)(v) << 1U) & FM_LPVD_CTL_TRIM)
#define GFV_LPVD_CTL_TRIM(v) \
  (((uint32)(v) & FM_LPVD_CTL_TRIM) >> 1U)

#define BM_LPVD_CTL_LPVD_EN  ((uint32)0x01U << 0U)

#define LPVD_CTL_2_OFF  0x34U

#define FM_LPVD_CTL_2_UV_SEL_33  ((uint32)0xffU << 16U)
#define FV_LPVD_CTL_2_UV_SEL_33(v) \
  (((uint32)(v) << 16U) & FM_LPVD_CTL_2_UV_SEL_33)
#define GFV_LPVD_CTL_2_UV_SEL_33(v) \
  (((uint32)(v) & FM_LPVD_CTL_2_UV_SEL_33) >> 16U)

#define FM_LPVD_CTL_2_OV_SEL_33  ((uint32)0xffU << 0U)
#define FV_LPVD_CTL_2_OV_SEL_33(v) \
  (((uint32)(v) << 0U) & FM_LPVD_CTL_2_OV_SEL_33)
#define GFV_LPVD_CTL_2_OV_SEL_33(v) \
  (((uint32)(v) & FM_LPVD_CTL_2_OV_SEL_33) >> 0U)

#define LPVD_CTL_3_OFF(n)  (0x38U + 4U*(n))

#define FM_LPVD_CTL_3_UV_SEL_33  ((uint32)0xffU << 16U)
#define FV_LPVD_CTL_3_UV_SEL_33(v) \
  (((uint32)(v) << 16U) & FM_LPVD_CTL_3_UV_SEL_33)
#define GFV_LPVD_CTL_3_UV_SEL_33(v) \
  (((uint32)(v) & FM_LPVD_CTL_3_UV_SEL_33) >> 16U)

#define FM_LPVD_CTL_3_OV_SEL_33  ((uint32)0xffU << 0U)
#define FV_LPVD_CTL_3_OV_SEL_33(v) \
  (((uint32)(v) << 0U) & FM_LPVD_CTL_3_OV_SEL_33)
#define GFV_LPVD_CTL_3_OV_SEL_33(v) \
  (((uint32)(v) & FM_LPVD_CTL_3_OV_SEL_33) >> 0U)

#define LPVD_STA_OFF  0x40U

#define BM_LPVD_STA_BGOK  ((uint32)0x01U << 31U)

#define BM_LPVD_STA_LPVD_NG_CLR  ((uint32)0x01U << 21U)

#define BM_LPVD_STA_LPVD_NG_STA  ((uint32)0x01U << 20U)

#define BM_LPVD_STA_AVDD_SAF_OV_STA  ((uint32)0x01U << 7U)

#define BM_LPVD_STA_AVDD_SAF_UV_STA  ((uint32)0x01U << 6U)

#define BM_LPVD_STA_VDD_SAF_OV_STA  ((uint32)0x01U << 5U)

#define BM_LPVD_STA_VDD_SAF_UV_STA  ((uint32)0x01U << 4U)

#define BM_LPVD_STA_AVDD_SAF_OV_MASK  ((uint32)0x01U << 3U)

#define BM_LPVD_STA_AVDD_SAF_UV_MASK  ((uint32)0x01U << 2U)

#define BM_LPVD_STA_VDD_SAF_OV_MASK  ((uint32)0x01U << 1U)

#define BM_LPVD_STA_VDD_SAF_UV_MASK  ((uint32)0x01U << 0U)

#define LPVD_STA_2_OFF(n)  (0x44U + 4U*(n))

#define BM_LPVD_STA_2_AVDD_LP_OV_STA  ((uint32)0x01U << 7U)

#define BM_LPVD_STA_2_AVDD_LP_UV_STA  ((uint32)0x01U << 6U)

#define BM_LPVD_STA_2_VDD_LP_OV_STA  ((uint32)0x01U << 5U)

#define BM_LPVD_STA_2_VDD_LP_UV_STA  ((uint32)0x01U << 4U)

#define BM_LPVD_STA_2_AVDD_LP_OV_MASK  ((uint32)0x01U << 3U)

#define BM_LPVD_STA_2_AVDD_LP_UV_MASK  ((uint32)0x01U << 2U)

#define BM_LPVD_STA_2_VDD_LP_OV_MASK  ((uint32)0x01U << 1U)

#define BM_LPVD_STA_2_VDD_LP_UV_MASK  ((uint32)0x01U << 0U)

#define PWR_DROP_PROT_OFF  0x50U

#define BM_PWR_DROP_PROT_UV_ADDR_CLR  ((uint32)0x01U << 31U)

#define FM_PWR_DROP_PROT_UV_ADDR_LAT  ((uint32)0x7fffU << 16U)
#define FV_PWR_DROP_PROT_UV_ADDR_LAT(v) \
  (((uint32)(v) << 16U) & FM_PWR_DROP_PROT_UV_ADDR_LAT)
#define GFV_PWR_DROP_PROT_UV_ADDR_LAT(v) \
  (((uint32)(v) & FM_PWR_DROP_PROT_UV_ADDR_LAT) >> 16U)

#define FM_PWR_DROP_PROT_UV_DGL_24M_CYCLE  ((uint32)0xffU << 8U)
#define FV_PWR_DROP_PROT_UV_DGL_24M_CYCLE(v) \
  (((uint32)(v) << 8U) & FM_PWR_DROP_PROT_UV_DGL_24M_CYCLE)
#define GFV_PWR_DROP_PROT_UV_DGL_24M_CYCLE(v) \
  (((uint32)(v) & FM_PWR_DROP_PROT_UV_DGL_24M_CYCLE) >> 8U)

#define BM_PWR_DROP_PROT_SAF_UV_CLK_SWITCH_CLR  ((uint32)0x01U << 5U)

#define BM_PWR_DROP_PROT_LP_UV_DGL_BYP  ((uint32)0x01U << 4U)

#define BM_PWR_DROP_PROT_SAF_UV_DGL_BYP  ((uint32)0x01U << 3U)

#define BM_PWR_DROP_PROT_SAF_UV_CLK_SWITCH_EN  ((uint32)0x01U << 2U)

#define BM_PWR_DROP_PROT_LP_UV_PROT_EN  ((uint32)0x01U << 1U)

#define BM_PWR_DROP_PROT_SAF_UV_PROT_EN  ((uint32)0x01U << 0U)

#define POR_CTRL_OFF  0x80U

#define BM_POR_CTRL_SYS_MODE_MASK  ((uint32)0x01U << 8U)

#define BM_POR_CTRL_POR_SYNC_EN  ((uint32)0x01U << 7U)

#define FM_POR_CTRL_POR_TEST  ((uint32)0x7U << 4U)
#define FV_POR_CTRL_POR_TEST(v) \
  (((uint32)(v) << 4U) & FM_POR_CTRL_POR_TEST)
#define GFV_POR_CTRL_POR_TEST(v) \
  (((uint32)(v) & FM_POR_CTRL_POR_TEST) >> 4U)

#define BM_POR_CTRL_POR_EN  ((uint32)0x01U << 0U)

#define POR_CTRL_2_OFF  0x84U

#define FM_POR_CTRL_2_BOR_SEL_33  ((uint32)0x3fU << 0U)
#define FV_POR_CTRL_2_BOR_SEL_33(v) \
  (((uint32)(v) << 0U) & FM_POR_CTRL_2_BOR_SEL_33)
#define GFV_POR_CTRL_2_BOR_SEL_33(v) \
  (((uint32)(v) & FM_POR_CTRL_2_BOR_SEL_33) >> 0U)

#define POR_CTRL_3_OFF(n)  (0x88U + 4U*(n))

#define FM_POR_CTRL_3_BOR_SEL_33  ((uint32)0xfU << 0U)
#define FV_POR_CTRL_3_BOR_SEL_33(v) \
  (((uint32)(v) << 0U) & FM_POR_CTRL_3_BOR_SEL_33)
#define GFV_POR_CTRL_3_BOR_SEL_33(v) \
  (((uint32)(v) & FM_POR_CTRL_3_BOR_SEL_33) >> 0U)

#define POR_STA_OFF  0x8cU

#define BM_POR_STA_AVDD_RTC_PORB_MASK  ((uint32)0x01U << 5U)

#define BM_POR_STA_AVDD_SAF_PORB_MASK  ((uint32)0x01U << 4U)

#define BM_POR_STA_VDD_SAF_PORB_MASK  ((uint32)0x01U << 3U)

#define BM_POR_STA_AVDD_RTC_PORB_STA  ((uint32)0x01U << 2U)

#define BM_POR_STA_AVDD_SAF_PORB_STA  ((uint32)0x01U << 1U)

#define BM_POR_STA_VDD_SAF_PORB_STA  ((uint32)0x01U << 0U)

#define POR_STA_2_OFF(n)  (0x90U + 4U*(n))

#define BM_POR_STA_2_AVDD_LP_PORB_MASK  ((uint32)0x01U << 3U)

#define BM_POR_STA_2_VDD_LP_PORB_MASK  ((uint32)0x01U << 2U)

#define BM_POR_STA_2_AVDD_LP_PORB_STA  ((uint32)0x01U << 1U)

#define BM_POR_STA_2_VDD_LP_PORB_STA  ((uint32)0x01U << 0U)

/* #define OSC_CHK_XTAL_EN_OFF  0x100U */

/* #define OSC_CHK_XTAL_CTL_OFF  0x104U */

/* #define OSC_CHK_XTAL_THRD_OFF  0x108U */

/* #define XTAL_CHK_OSC_EN_OFF  0x200U */

/* #define XTAL_CHK_OSC_CTL_OFF  0x204U */

/* #define XTAL_CHK_OSC_THRD_OFF  0x208U */

/* #define ERR_INJ_EN_OFF(n)  (0x600U + 16U*(n)) */

/* #define FS_WDAT_ERR_INJ_OFF(n)  (0x604U + 16U*(n)) */

/* #define FS_WECC_ERR_INJ_OFF(n)  (0x608U + 16U*(n)) */

/* #define FS_APB_ERR_INT_OFF(n)  (0x610U + 16U*(n)) */

/* #define FS_FUSA_INT_OFF  0x614U */

#define BM_FS_FUSA_INT_LPVD_NG_EN  ((uint32)0x01U << 4U)

/* #define FS_ERR_INJ_OFF(n)  (0x618U + 4U*(n)) */

#define BM_FS_ERR_INJ_LPVD_NG_INJ  ((uint32)0x01U << 3U)

#define FS_FUNC_INT_OFF  0x620U

#define BM_FS_FUNC_INT_XTAL_RDY_INT_STA  ((uint32)0x01U << 8U)

#define BM_FS_FUNC_INT_LPVD_NG_INT_EN  ((uint32)0x01U << 1U)

#define BM_FS_FUNC_INT_XTAL_RDY_INT_EN  ((uint32)0x01U << 0U)

/* #define FS_PRDATAINJ_OFF(n)  (0x700U + 12U*(n)) */

/* #define FS_REG_PARITY_ERR_INT_STAT_OFF(n)  (0x704U + 12U*(n)) */

/* #define FS_REG_PARITY_ERR_INT_SIG_EN_OFF(n)  (0x708U + 12U*(n)) */

/* FS24M */

#define FS_GLB_CTL_OFF  0x0U

#define BM_FS_GLB_CTL_XTAL_ACTIVE  ((uint32)0x01U << 31U)

#define BM_FS_GLB_CTL_RC_ACTIVE  ((uint32)0x01U << 30U)

#define BM_FS_GLB_CTL_XTAL_RDY  ((uint32)0x01U << 29U)

#define BM_FS_GLB_CTL_RC_RDY  ((uint32)0x01U << 28U)

#define BM_FS_GLB_CTL_XTAL_FORCE_DIS  ((uint32)0x01U << 20U)

#define BM_FS_GLB_CTL_FS_SRC_SEL_LOCK  ((uint32)0x01U << 19U)

#define BM_FS_GLB_CTL_HIB_EXP  ((uint32)0x01U << 17U)

#define BM_FS_GLB_CTL_SLP_EXP  ((uint32)0x01U << 16U)

#define BM_FS_GLB_CTL_CMP_FORCE_CLR  ((uint32)0x01U << 8U)

#define BM_FS_GLB_CTL_EXT_OSC_EN  ((uint32)0x01U << 5U)

#define BM_FS_GLB_CTL_EXT_XTAL_EN  ((uint32)0x01U << 4U)

#define BM_FS_GLB_CTL_FS_OSC_EN  ((uint32)0x01U << 3U)

#define BM_FS_GLB_CTL_FS_XTAL_EN  ((uint32)0x01U << 2U)

#define BM_FS_GLB_CTL_FS_SRC_SEL  ((uint32)0x01U << 1U)

#define BM_FS_GLB_CTL_XTAL_SRC_SEL  ((uint32)0x01U << 0U)

#define RC_CTL_OFF  0x10U

#define FM_RC_CTL_FREQ_TUNE_B  ((uint32)0xffU << 0U)
#define FV_RC_CTL_FREQ_TUNE_B(v) \
  (((uint32)(v) << 0U) & FM_RC_CTL_FREQ_TUNE_B)
#define GFV_RC_CTL_FREQ_TUNE_B(v) \
  (((uint32)(v) & FM_RC_CTL_FREQ_TUNE_B) >> 0U)

#define RC_RES_OFF  0x14U

#define FM_RC_RES_RES  ((uint32)0xffffffffU << 0U)
#define FV_RC_RES_RES(v) \
  (((uint32)(v) << 0U) & FM_RC_RES_RES)
#define GFV_RC_RES_RES(v) \
  (((uint32)(v) & FM_RC_RES_RES) >> 0U)

#define BM_XTAL_CTL_OFF  0x20U

#define BM_XTAL_CTL_XTAL_RDY_DLY  ((uint32)0x01U << 6U)

#define BM_XTAL_CTL_POE  ((uint32)0x01U << 5U)

#define BM_XTAL_CTL_SP  ((uint32)0x01U << 4U)

#define FM_XTAL_CTL_SF  ((uint32)0x3U << 2U)
#define FV_XTAL_CTL_SF(v) \
  (((uint32)(v) << 2U) & FM_XTAL_CTL_SF)
#define GFV_XTAL_CTL_SF(v) \
  (((uint32)(v) & FM_XTAL_CTL_SF) >> 2U)

#define BM_XTAL_CTL_TE  ((uint32)0x01U << 1U)

#define BM_XTAL_CTL_E0  ((uint32)0x01U << 0U)

#define XTAL_RES_OFF  0x24U

#define FM_XTAL_RES_RES  ((uint32)0xffffffffU << 0U)
#define FV_XTAL_RES_RES(v) \
  (((uint32)(v) << 0U) & FM_XTAL_RES_RES)
#define GFV_XTAL_RES_RES(v) \
  (((uint32)(v) & FM_XTAL_RES_RES) >> 0U)

#define XTAL_DIV_CONFIG_OFF  0x28U

#define BM_XTAL_DIV_CONFIG_XTAL_DIV2_LOCK  ((uint32)0x01U << 31U)

#define BM_XTAL_DIV_CONFIG_XTAL_AUTO_DIV2_IND  ((uint32)0x01U << 30U)

#define BM_XTAL_DIV_CONFIG_XTAL_AUTO_DET_DONE  ((uint32)0x01U << 29U)

#define BM_XTAL_DIV_CONFIG_XTAL_DIV_FORCE  ((uint32)0x01U << 1U)

#define BM_XTAL_DIV_CONFIG_XTAL_DIV2  ((uint32)0x01U << 0U)

#define OSC_CHK_XTAL_EN_OFF  0x100U

#define BM_OSC_CHK_XTAL_EN_FORCE_CHK_EN_STA  ((uint32)0x01U << 31U)

#define BM_OSC_CHK_XTAL_EN_HW_CHK_EN_STA  ((uint32)0x01U << 30U)

#define BM_OSC_CHK_XTAL_EN_FORCE_CHK_EN  ((uint32)0x01U << 1U)

#define BM_OSC_CHK_XTAL_EN_HW_CHK_EN  ((uint32)0x01U << 0U)

#define OSC_CHK_XTAL_CTL_OFF  0x104U

#define BM_OSC_CHK_XTAL_CTL_CLK_NG_MON  ((uint32)0x01U << 31U)

#define FM_OSC_CHK_XTAL_CTL_CHK_CFG  ((uint32)0xffffU << 3U)
#define FV_OSC_CHK_XTAL_CTL_CHK_CFG(v) \
  (((uint32)(v) << 3U) & FM_OSC_CHK_XTAL_CTL_CHK_CFG)
#define GFV_OSC_CHK_XTAL_CTL_CHK_CFG(v) \
  (((uint32)(v) & FM_OSC_CHK_XTAL_CTL_CHK_CFG) >> 3U)

#define FM_OSC_CHK_XTAL_CTL_EXT_CFG  ((uint32)0x7U << 0U)
#define FV_OSC_CHK_XTAL_CTL_EXT_CFG(v) \
  (((uint32)(v) << 0U) & FM_OSC_CHK_XTAL_CTL_EXT_CFG)
#define GFV_OSC_CHK_XTAL_CTL_EXT_CFG(v) \
  (((uint32)(v) & FM_OSC_CHK_XTAL_CTL_EXT_CFG) >> 0U)

#define OSC_CHK_XTAL_THRD_OFF  0x108U

#define FM_OSC_CHK_XTAL_THRD_HIGH  ((uint32)0xffffU << 16U)
#define FV_OSC_CHK_XTAL_THRD_HIGH(v) \
  (((uint32)(v) << 16U) & FM_OSC_CHK_XTAL_THRD_HIGH)
#define GFV_OSC_CHK_XTAL_THRD_HIGH(v) \
  (((uint32)(v) & FM_OSC_CHK_XTAL_THRD_HIGH) >> 16U)

#define FM_OSC_CHK_XTAL_THRD_LOW  ((uint32)0xffffU << 0U)
#define FV_OSC_CHK_XTAL_THRD_LOW(v) \
  (((uint32)(v) << 0U) & FM_OSC_CHK_XTAL_THRD_LOW)
#define GFV_OSC_CHK_XTAL_THRD_LOW(v) \
  (((uint32)(v) & FM_OSC_CHK_XTAL_THRD_LOW) >> 0U)

#define XTAL_CHK_OSC_EN_OFF  0x200U

#define BM_XTAL_CHK_OSC_EN_FORCE_CHK_EN_STA  ((uint32)0x01U << 31U)

#define BM_XTAL_CHK_OSC_EN_HW_CHK_EN_STA  ((uint32)0x01U << 30U)

#define BM_XTAL_CHK_OSC_EN_FORCE_CHK_EN  ((uint32)0x01U << 1U)

#define BM_XTAL_CHK_OSC_EN_HW_CHK_EN  ((uint32)0x01U << 0U)

#define XTAL_CHK_OSC_CTL_OFF  0x204U

#define BM_XTAL_CHK_OSC_CTL_CLK_NG_MON  ((uint32)0x01U << 31U)

#define FM_XTAL_CHK_OSC_CTL_CHK_CFG  ((uint32)0xffffU << 3U)
#define FV_XTAL_CHK_OSC_CTL_CHK_CFG(v) \
  (((uint32)(v) << 3U) & FM_XTAL_CHK_OSC_CTL_CHK_CFG)
#define GFV_XTAL_CHK_OSC_CTL_CHK_CFG(v) \
  (((uint32)(v) & FM_XTAL_CHK_OSC_CTL_CHK_CFG) >> 3U)

#define FM_XTAL_CHK_OSC_CTL_EXT_CFG  ((uint32)0x7U << 0U)
#define FV_XTAL_CHK_OSC_CTL_EXT_CFG(v) \
  (((uint32)(v) << 0U) & FM_XTAL_CHK_OSC_CTL_EXT_CFG)
#define GFV_XTAL_CHK_OSC_CTL_EXT_CFG(v) \
  (((uint32)(v) & FM_XTAL_CHK_OSC_CTL_EXT_CFG) >> 0U)

#define XTAL_CHK_OSC_THRD_OFF  0x208U

#define FM_XTAL_CHK_OSC_THRD_HIGH  ((uint32)0xffffU << 16U)
#define FV_XTAL_CHK_OSC_THRD_HIGH(v) \
  (((uint32)(v) << 16U) & FM_XTAL_CHK_OSC_THRD_HIGH)
#define GFV_XTAL_CHK_OSC_THRD_HIGH(v) \
  (((uint32)(v) & FM_XTAL_CHK_OSC_THRD_HIGH) >> 16U)

#define FM_XTAL_CHK_OSC_THRD_LOW  ((uint32)0xffffU << 0U)
#define FV_XTAL_CHK_OSC_THRD_LOW(v) \
  (((uint32)(v) << 0U) & FM_XTAL_CHK_OSC_THRD_LOW)
#define GFV_XTAL_CHK_OSC_THRD_LOW(v) \
  (((uint32)(v) & FM_XTAL_CHK_OSC_THRD_LOW) >> 0U)

#define EXT_CHK_XTAL_EN_OFF  0x300U

#define BM_EXT_CHK_XTAL_EN_FORCE_CHK_EN_STA  ((uint32)0x01U << 31U)

#define BM_EXT_CHK_XTAL_EN_HW_CHK_EN_STA  ((uint32)0x01U << 30U)

#define BM_EXT_CHK_XTAL_EN_FORCE_CHK_EN  ((uint32)0x01U << 1U)

#define BM_EXT_CHK_XTAL_EN_HW_CHK_EN  ((uint32)0x01U << 0U)

#define EXT_CHK_XTAL_CTL_OFF  0x304U

#define BM_EXT_CHK_XTAL_CTL_CLK_NG_MON  ((uint32)0x01U << 31U)

#define FM_EXT_CHK_XTAL_CTL_CHK_CFG  ((uint32)0xffffU << 3U)
#define FV_EXT_CHK_XTAL_CTL_CHK_CFG(v) \
  (((uint32)(v) << 3U) & FM_EXT_CHK_XTAL_CTL_CHK_CFG)
#define GFV_EXT_CHK_XTAL_CTL_CHK_CFG(v) \
  (((uint32)(v) & FM_EXT_CHK_XTAL_CTL_CHK_CFG) >> 3U)

#define FM_EXT_CHK_XTAL_CTL_EXT_CFG  ((uint32)0x7U << 0U)
#define FV_EXT_CHK_XTAL_CTL_EXT_CFG(v) \
  (((uint32)(v) << 0U) & FM_EXT_CHK_XTAL_CTL_EXT_CFG)
#define GFV_EXT_CHK_XTAL_CTL_EXT_CFG(v) \
  (((uint32)(v) & FM_EXT_CHK_XTAL_CTL_EXT_CFG) >> 0U)

#define EXT_CHK_XTAL_THRD_OFF  0x308U

#define FM_EXT_CHK_XTAL_THRD_HIGH  ((uint32)0xffffU << 16U)
#define FV_EXT_CHK_XTAL_THRD_HIGH(v) \
  (((uint32)(v) << 16U) & FM_EXT_CHK_XTAL_THRD_HIGH)
#define GFV_EXT_CHK_XTAL_THRD_HIGH(v) \
  (((uint32)(v) & FM_EXT_CHK_XTAL_THRD_HIGH) >> 16U)

#define FM_EXT_CHK_XTAL_THRD_LOW  ((uint32)0xffffU << 0U)
#define FV_EXT_CHK_XTAL_THRD_LOW(v) \
  (((uint32)(v) << 0U) & FM_EXT_CHK_XTAL_THRD_LOW)
#define GFV_EXT_CHK_XTAL_THRD_LOW(v) \
  (((uint32)(v) & FM_EXT_CHK_XTAL_THRD_LOW) >> 0U)

#define EXT_CHK_OSC_EN_OFF  0x400U

#define BM_EXT_CHK_OSC_EN_FORCE_CHK_EN_STA  ((uint32)0x01U << 31U)

#define BM_EXT_CHK_OSC_EN_HW_CHK_EN_STA  ((uint32)0x01U << 30U)

#define BM_EXT_CHK_OSC_EN_FORCE_CHK_EN  ((uint32)0x01U << 1U)

#define BM_EXT_CHK_OSC_EN_HW_CHK_EN  ((uint32)0x01U << 0U)

#define EXT_CHK_OSC_CTL_OFF  0x404U

#define BM_EXT_CHK_OSC_CTL_CLK_NG_MON  ((uint32)0x01U << 31U)

#define FM_EXT_CHK_OSC_CTL_CHK_CFG  ((uint32)0xffffU << 3U)
#define FV_EXT_CHK_OSC_CTL_CHK_CFG(v) \
  (((uint32)(v) << 3U) & FM_EXT_CHK_OSC_CTL_CHK_CFG)
#define GFV_EXT_CHK_OSC_CTL_CHK_CFG(v) \
  (((uint32)(v) & FM_EXT_CHK_OSC_CTL_CHK_CFG) >> 3U)

#define FM_EXT_CHK_OSC_CTL_EXT_CFG  ((uint32)0x7U << 0U)
#define FV_EXT_CHK_OSC_CTL_EXT_CFG(v) \
  (((uint32)(v) << 0U) & FM_EXT_CHK_OSC_CTL_EXT_CFG)
#define GFV_EXT_CHK_OSC_CTL_EXT_CFG(v) \
  (((uint32)(v) & FM_EXT_CHK_OSC_CTL_EXT_CFG) >> 0U)

#define EXT_CHK_OSC_THRD_OFF  0x408U

#define FM_EXT_CHK_OSC_THRD_HIGH  ((uint32)0xffffU << 16U)
#define FV_EXT_CHK_OSC_THRD_HIGH(v) \
  (((uint32)(v) << 16U) & FM_EXT_CHK_OSC_THRD_HIGH)
#define GFV_EXT_CHK_OSC_THRD_HIGH(v) \
  (((uint32)(v) & FM_EXT_CHK_OSC_THRD_HIGH) >> 16U)

#define FM_EXT_CHK_OSC_THRD_LOW  ((uint32)0xffffU << 0U)
#define FV_EXT_CHK_OSC_THRD_LOW(v) \
  (((uint32)(v) << 0U) & FM_EXT_CHK_OSC_THRD_LOW)
#define GFV_EXT_CHK_OSC_THRD_LOW(v) \
  (((uint32)(v) & FM_EXT_CHK_OSC_THRD_LOW) >> 0U)

#define RC32K_CHK_CTL_OFF  0x500U

#define FM_RC32K_CHK_CTL_FREQ_CNT_STA  ((uint32)0xffffU << 16U)
#define FV_RC32K_CHK_CTL_FREQ_CNT_STA(v) \
  (((uint32)(v) << 16U) & FM_RC32K_CHK_CTL_FREQ_CNT_STA)
#define GFV_RC32K_CHK_CTL_FREQ_CNT_STA(v) \
  (((uint32)(v) & FM_RC32K_CHK_CTL_FREQ_CNT_STA) >> 16U)

#define BM_RC32K_CHK_CTL_FREQ_VIO_CLR  ((uint32)0x01U << 3U)

#define BM_RC32K_CHK_CTL_FREQ_VIO_STA  ((uint32)0x01U << 2U)

#define BM_RC32K_CHK_CTL_MON_EN_STA  ((uint32)0x01U << 1U)

#define BM_RC32K_CHK_CTL_MON_EN  ((uint32)0x01U << 0U)

#define RC32K_CHK_THRD_OFF  0x508U

#define FM_RC32K_CHK_THRD_HIGH  ((uint32)0xffffU << 16U)
#define FV_RC32K_CHK_THRD_HIGH(v) \
  (((uint32)(v) << 16U) & FM_RC32K_CHK_THRD_HIGH)
#define GFV_RC32K_CHK_THRD_HIGH(v) \
  (((uint32)(v) & FM_RC32K_CHK_THRD_HIGH) >> 16U)

#define FM_RC32K_CHK_THRD_LOW  ((uint32)0xffffU << 0U)
#define FV_RC32K_CHK_THRD_LOW(v) \
  (((uint32)(v) << 0U) & FM_RC32K_CHK_THRD_LOW)
#define GFV_RC32K_CHK_THRD_LOW(v) \
  (((uint32)(v) & FM_RC32K_CHK_THRD_LOW) >> 0U)

#define BM_ERR_INJ_EN_OFF(n)  (0x600U + 16U*(n))

#define BM_ERR_INJ_EN_OUT_INJ_EN  ((uint32)0x01U << 2U)

#define BM_ERR_INJ_EN_IRQ_INJ_EN  ((uint32)0x01U << 1U)

#define BM_ERR_INJ_EN_APB_INJ_EN  ((uint32)0x01U << 0U)

#define FS_WDAT_ERR_INJ_OFF(n)  (0x604U + 16U*(n))

#define FS_WECC_ERR_INJ_OFF(n)  (0x608U + 16U*(n))

#define FS_APB_ERR_INT_OFF(n)  (0x610U + 16U*(n))

#define FS_FUSA_INT_OFF  0x614U

#define BM_FS_FUSA_INT_SWITCH_ERR_CLR  ((uint32)0x01U << 21U)

#define BM_FS_FUSA_INT_EXT_CHK_OSC_NG_CLR  ((uint32)0x01U << 20U)

#define BM_FS_FUSA_INT_EXT_CHK_XTAL_NG_CLR  ((uint32)0x01U << 19U)

#define BM_FS_FUSA_INT_XTAL_CHK_OSC_NG_CLR  ((uint32)0x01U << 18U)

#define BM_FS_FUSA_INT_OSC_CHK_XTAL_NG_CLR  ((uint32)0x01U << 17U)

#define BM_FS_FUSA_INT_SYNC_ERR_CLR  ((uint32)0x01U << 16U)

#define BM_FS_FUSA_INT_SWITCH_ERR_STA  ((uint32)0x01U << 13U)

#define BM_FS_FUSA_INT_EXT_CHK_OSC_NG_STA  ((uint32)0x01U << 12U)

#define BM_FS_FUSA_INT_EXT_CHK_XTAL_NG_STA  ((uint32)0x01U << 11U)

#define BM_FS_FUSA_INT_XTAL_CHK_OSC_NG_STA  ((uint32)0x01U << 10U)

#define BM_FS_FUSA_INT_OSC_CHK_XTAL_NG_STA  ((uint32)0x01U << 9U)

#define BM_FS_FUSA_INT_SYNC_ERR_STA  ((uint32)0x01U << 8U)

#define BM_FS_FUSA_INT_SWITCH_ERR_EN  ((uint32)0x01U << 5U)

#define BM_FS_FUSA_INT_EXT_CHK_OSC_NG_EN  ((uint32)0x01U << 4U)

#define BM_FS_FUSA_INT_EXT_CHK_XTAL_NG_EN  ((uint32)0x01U << 3U)

#define BM_FS_FUSA_INT_XTAL_CHK_OSC_NG_EN  ((uint32)0x01U << 2U)

#define BM_FS_FUSA_INT_OSC_CHK_XTAL_NG_EN  ((uint32)0x01U << 1U)

#define BM_FS_FUSA_INT_SYNC_ERR_EN  ((uint32)0x01U << 0U)

#define FS_ERR_INJ_OFF(n)  (0x618U + 4U*(n))

#define BM_FS_ERR_INJ_UNC_IRQ_INJ  ((uint32)0x01U << 2U)

#define BM_FS_ERR_INJ_COR_IRQ_INJ  ((uint32)0x01U << 1U)

#define BM_FS_ERR_INJ_FS_IRQ_INJ  ((uint32)0x01U << 0U)

#define FS_PRDATAINJ_OFF(n)  (0x700U + 12U*(n))

#define FS_REG_PARITY_ERR_INT_STAT_OFF(n)  (0x704U + 12U*(n))

#define FS_REG_PARITY_ERR_INT_SIG_EN_OFF(n)  (0x708U + 12U*(n))

#ifdef __cplusplus
}
#endif


#endif /* XTAL_REG_H */
/* End of file */
